1. Field of the Invention
The present invention relates to a data transfer circuit provided in a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit is provided with various internal circuits. Data transfer between such internal circuits is performed based on transfer signals output from a data transfer control circuit. With acceleration of the operational speeds of semiconductor integrated circuits, it is required to increase the rate of data transfer. It is an utmost necessity to prevent erroneous data transfer operation caused by transfer control signals input at different timings.
FIG. 1 schematically shows a conventional data transfer device. The data transfer device formed in a semiconductor integrated circuit includes a data generating circuit 1 and a data latch circuit 2. The data generating circuit 1 receives an externally supplied transfer signal TR, and generates a data signal in response to the signal TR. The generated data is supplied to the data latch circuit 2. The data latch circuit 2 latches the data from the data generating circuit 1 in accordance with a data latch signal DL. The latched data is output therefrom as an output data Dout.
If a great discrepancy between timings of the transfer signal TR and the data latch signal DL occurs due to an increase in data transfer rate, it is possible that the data latch circuit 2 does not output an exact output data Dout. In other words, before the data input to the data latch circuit 2 from the data generating circuit 1 has been stabilized, a data latch signal DL may be input to the data latch circuit 2. In this case, an unstable data signal will unfortunately be latched by the latch circuit 2.